In communications systems, data is transmitted at high speed. Sometimes the speed of the communication means is higher than that of the data to be transmitted over them. In order to utilize the entire speed of the communication system, a plurality of relatively low speed data signals can be mixed to a single high speed signal, by alternating between them. This method is called interleaving.
For example, four data signals of 10 GHz each can be mixed to a single 40 GHz transmission signal, whereas a quarter of the transmission signal's time space is allocated to each data signal.
High speed DACs are often constructed in a time interleaved fashion, in which data signals are processed and finally multiplexed together, to form a higher speed transmission signal.
Typical time interleaved DACs are constructed as “half rate” or “quarter rate”, thereby implying the amount of time space allocated for each data signal in the transmission signal.
The timing and synchronization of the data signals are controlled by a timing circuit, e.g. a PLL, which supplies a clock signal for each data signal at the frequency of the data signals, fd. Each clock signal is introduced with a time difference of
  1            f      d        *    x  seconds relative to the other clock signals, wherein x is the order of modulation. In the example above, the four data signals of 10 GHz are each provided with a clock signal of 10 GHz with a time difference of 25 picoseconds between each other. This introduces each data signal a time space sufficient to its frequency, while not overlapping other data signals.
Due to imperfections in analog and digital circuitry, the lower rate data signals are normally not multiplexed with perfect spaced timing. This imperfect spaced timing introduces distortion and degrades the Signal-to-total-Noise and Distortion Ratio (SNDR), which can also be seen on an eye diagram.
An eye diagram is a methodology to represent and analyze high speed digital signals (such as optical and base band signals), their quality and the ability to perform clock and data recovery. For all waveforms, the eye diagram allows parameters of the electrical quality of the signal to be visualized. The data eye diagram is constructed from a digital waveform by folding the parts of the waveform corresponding to each individual symbol into a single graph with signal amplitude on the vertical axis and time on horizontal axis. This construction is repeated over many samples of the waveform, the resultant graph will represent the average statistics of the signal and will resemble an eye. The eye opening corresponds to one symbol period and is typically called the Unit Interval (UI) width of the eye diagram. The eye diagram offers additional information beyond the time domain waveform display, including impairments such as attenuation, noise, crosstalk, etc.
FIG. 1. (prior art) illustrates an EYE diagram of a PAM-4 quarter-rate DAC with interleaved timing errors. Unequal eye widths and heights are visible. These distortions and degradations, introduced by imperfect timing, are related to as interleaved timing errors.
Interleaved timing errors can vary in a number of manners:    differences between data signal time frames;    differences between DACs;    differences between dies; and    differences between processes, operating temperatures, power supply voltages etc., which appear over time.
Calibration of interleaved timing errors and of the systems which produce them, can be performed using a method called “foreground calibration”, according to which special test signals are introduced at each of the data signal inputs and are tested for time optimization. This method introduces a period of time at which the DAC is not resolving true input data signals, which is not acceptable for some applications. In addition foreground calibration introduces slowdown in the final data transmission.
Another existing method for calibrating interleaved timing errors is by using special circuitry. However, this solution is expensive in terms of die area or power dissipation.
An alternative method is a onetime calibration (e.g., at power-up), where the calibration scheme does not interfere with the transmission scheme once the latter has begun. This method however is not optimal, since the calibration will degrade over time, which entails SNDR degradation over time, when the errors themselves change over time, due to the fact that temperature or other condition changes.
It would be advantageous to calibrate time interleaved errors without interfering normal data transmission, while maintaining calibration throughout the entire transmission scheme, using an economical system.
It is therefore an object of the present invention to provide a method and system for calibrating time interleave errors without interfering data transmission, while maintaining calibration throughout the whole transmission scheme, using an economical system.
Other objects and advantages of this invention will become apparent as the description proceeds.